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LTC2309 1 2309f block diagram features applications description 8-channel, 12-bit sar adc with i 2 c interface n industrial process control n motor control n accelerometer measurements n battery-operated instruments n isolated and/or remote data acquisition n power supply monitoring l , lt, ltc and ltm are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. integral nonlinearity vs output code n 12-bit resolution n low power: 1.5mw at 1ksps, 35w sleep mode n 14ksps throughput rate n low noise: snr = 73.4db n guaranteed no missing codes n single 5v supply n 2-wire i 2 c compatible serial interface with nine addresses plus one global for synchronization n fast conversion time: 1.3s n internal reference n internal 8-channel multiplexer n internal conversion clock n unipolar or bipolar input ranges (software selectable) n 24-pin 4mm 4mm qfn package the ltc ? 2309 is a low noise, low power, 8-channel, 12-bit successive approximation adc with an i 2 c compatible serial interface. this adc includes an internal reference and a fully differential sample-and-hold circuit to reduce common mode noise. the LTC2309 operates from an internal clock to achieve a fast 1.3s conversion time. the LTC2309 operates from a single 5v supply and draws just 300a at a throughput rate of 1ksps. the adc enters nap mode when not converting, reducing the power dissipation. the LTC2309 is available in a small 24-pin 4mm 4mm qfn package. the internal 2.5v reference and 8-channel multiplexer further reduce pcb board space require- ments. the low power consumption and small size make the LTC2309 ideal for battery-operated and portable applica- tions, while the 2-wire i 2 c compatible serial interface makes this adc a good match for space-constrained systems. ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 com 2309 ta01 i 2 c port analog input mux analog inputs 0v to 4.096v unipolar 2.048v bipolar refcomp internal 2.5v ref av dd dv dd 5v gnd LTC2309 0.1 f 12-bit sar adc + C 2.2f 10f 0.1 f 10f 0.1 f 10f v ref sda scl ad1 ad0 output code 0 inl (lsb) 0 0.25 0.50 4096 2309 g01 C0.25 C0.50 C1.00 1024 2048 3072 C0.75 1.00 0.75
LTC2309 2 2309f absolute maximum ratings (notes 1, 2) order information lead free finish tape and reel part marking* package description temperature range LTC2309cuf#pbf LTC2309cuf#trpbf 2309 24-lead (4mm 4mm) plastic qfn 0c to 70c LTC2309iuf#pbf LTC2309iuf#trpbf 2309 24-lead (4mm 4mm) plastic qfn C40c to 85c consult ltc marketing for parts speci? ed with wider operating temperature ranges. *the temperature grade is identi? ed by a label on the shipping container. consult ltc marketing for information on non-standard lead based ? nish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/ supply voltage (av dd , dv dd ) ...................... C0.3v to 6v analog input voltage (note 3) ch0-ch7, com, v ref , refcomp ...................(gnd C 0.3v) to (av dd + 0.3v) digital input voltage (note 3) .................(gnd C 0.3v) to (dv dd + 0.3v) digital output voltage .... (gnd C 0.3v) to (dv dd + 0.3v) power dissipation ...............................................500mw operating temperature range LTC2309c ................................................ 0c to 70c LTC2309i.............................................. C40c to 85c storage temperature range ................... C65c to 150c pin configuration 24 25 23 22 21 20 19 7 8 9 top view uf package 24-lead (4mm s 4mm) plastic qfn 10 11 12 6 5 4 3 2 1 13 14 15 16 17 18 ch3 ch4 ch5 ch6 ch7 com gnd sda scl ad1 ad0 av dd ch2 ch1 ch0 dv dd gnd gnd v ref refcomp gnd gnd gnd av dd t jmax = 150c, ja = 37c/w exposed pad (pin 25) is gnd, must be soldered to pcb
LTC2309 3 2309f converter and multiplexer characteristics parameter conditions min typ max units resolution (no missing codes) l 12 bits integral linearity error (note 6) l 0.45 1 lsb differential linearity error l 0.35 1 lsb bipolar zero error (note 7) l 1 8 lsb bipolar zero error drift 0.002 lsb/c bipolar zero error match 0.1 3 lsb unipolar zero error (note 7) l 0.4 6 lsb unipolar zero error drift 0.002 lsb/c unipolar zero error match 0.2 1 lsb bipolar full-scale error external reference (note 8) refcomp = 4.096v l l 0.5 0.4 10 9 lsb lsb bipolar full-scale error drift external reference 0.05 lsb/c bipolar full-scale error match 0.4 3 lsb unipolar full-scale error external reference (note 8) refcomp = 4.096v l l 0.4 0.3 10 6 lsb lsb unipolar full-scale error drift external reference 0.05 lsb/c unipolar full-scale error match 0.3 2 lsb the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (notes 4, 5) symbol parameter conditions min typ max units v in + absolute input range (ch0 to ch7) (note 9) l C0.05 av dd v v in C absolute input range (ch0 to ch7, com) unipolar (note 9) bipolar (note 9) l l C0.05 C0.05 av dd /2 av dd v v v in + C v in C input differential voltage range v in = v in + C v in C (unipolar) v in = v in + C v in C (bipolar) l l 0 to refcomp refcomp/2 v v i in analog input leakage current l 1 a c in analog input capacitance sample mode hold mode 55 5 pf pf cmrr input common mode rejection ratio 70 db analog input the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) symbol parameter conditions min typ max units sinad signal-to-(noise + distortion) ratio f in = 1khz l 71 73.3 db snr signal-to-noise ratio f in = 1khz l 71 73.4 db thd total harmonic distortion f in = 1khz, first 5 harmonics l C88 C77 db sfdr spurious free dynamic range f in = 1khz l 79 90 db channel-to-channel isolation f in = 1khz C109 db full linear bandwidth (note 11) 700 khz C3db input linear bandwidth 25 mhz aperature delay 13 ns transient response full-scale step 240 ns dynamic accuracy the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. a in = C1dbfs. (notes 4, 10)
LTC2309 4 2309f power requirements parameter conditions min typ max units v ref output voltage i out = 0 l 2.47 2.50 2.53 v v ref output tempco i out = 0 25 ppm/c v ref output impedance C0.1ma i out 0.1ma 8 k v refcomp output voltage i out = 0 4.096 v v ref line regulation av dd = 4.75v to 5.25v 0.8 mv/v internal reference characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) i 2 c inputs and digital outputs the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) symbol parameter conditions min typ max units v ih high level input voltage l 0.7v cc v v il low level input voltage l 0.3v cc v v iha high level input voltage for address pins a1, a0 l 0.95v cc v v ila low level input voltage for address pins a1, a0 l 0.05v cc v r inh resistance from a1, a0, to v cc to set chip address bit to 1 l 10 k r inl resistance from a1, a0 to gnd to set chip address bit to 0 l 10 k r inf resistance from a1, a0 to gnd or v cc to set chip address bit to float l 2m i i digital input current l C10 10 a v hys hysteresis of schmitt trigger inputs (note 9) l 0.05v cc v v ol low level output voltage (sda) i = 3ma l 0.4 v t of output fall time v h to v il(max) (note 12) l 20 + 0.1c b 250 ns t sp input spike suppression l 50 ns c cax external capacitance load on chip address pins (a1, a0) for valid float l 10 pf symbol parameter conditions min typ max units av dd analog supply voltage l 4.75 5 5.25 v dv dd digital supply voltage l 4.75 5 5.25 v i dd supply current nap mode sleep mode 14ksps sample rate slp bit = 0, conversion done slp bit = 1, conversion done l l l 2.3 210 7 3 350 15 ma a a p d power dissipation nap mode sleep mode 14ksps sample rate slp bit = 0, conversion done slp bit = 1, conversion done 11.5 1.05 35 15 1.75 75 mw mw w the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4)
LTC2309 5 2309f i 2 c timing characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) symbol parameter conditions min typ max units f scl scl clock frequency l 400 khz t hd(sda) hold time (repeated) start condition l 0.6 s t low low period of the scl pin l 1.3 s t high high period of the scl pin l 0.6 s t su(sta) set-up time for a repeated start condition l 0.6 s t hd(dat) data hold time l 0 0.9 s t su(dat) data set-up time l 100 ns t r rise time for sda/scl signals (note 12) l 20 + 0.1c b 300 ns t f fall time for sda/scl signals (note 12) l 20 + 0.1c b 300 ns t su(sto) set-up time for stop condition l 0.6 s t buf bus free time between a stop and start condition l 1.3 s adc timing characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) symbol parameter conditions min typ max units f smpl throughput rate (successive reads) l 14 ksps t conv conversion time (note 9) l 1.3 1.8 s t acq acquisition time (note 9) l 240 ns t refwake refcomp wake-up time (note 13) c refcomp = 10f, c ref = 2.2f 200 ms note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to ground with av dd and dv dd wired together (unless otherwise noted). note 3: when these pin voltages are taken below ground or above v dd , they will be clamped by internal diodes. these products can handle input currents greater than 100ma below ground or above v dd without latchup. note 4: av dd = 5v, dv dd = 5v, f smpl = 14ksps internal reference unless otherwise noted. note 5: linearity, offset and full-scale speci? cations apply for a single-ended analog input with respect to com. note 6: integral nonlinearity is de? ned as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 7: bipolar zero error is the offset voltage measured from C0.5lsb when the output code ? ickers between 0000 0000 0000 and 1111 1111 1111. unipolar zero error is the offset voltage measured from +0.5lsb when the output code ? ickers between 0000 0000 0000 and 0000 0000 0001. note 8: full-scale bipolar error is the worst-case of Cfs or +fs untrimmed deviation from ideal ? rst and last code transitions and includes the effect of offset error. unipolar full-scale error is the deviation of the last code transition from ideal and includes the effect of offset error. note 9: guaranteed by design, not subject to test. note 10: all speci? cations in db are referred to a full-scale 2.048v input with a 2.5v reference voltage. note 11: full linear bandwidth is de? ned as the full-scale input frequency at which the sinad degrades to 60db or 10 bits of accuracy. note 12: c b = capacitance of one bus line in pf (10pf c b 400pf). note 13: refcomp wake-up time is the time required for the refcomp pin to settle within 0.5lsb at 12-bit resolution of its ? nal value after waking up from sleep mode.
LTC2309 6 2309f typical performance characteristics integral nonlinearity vs output code 1khz sine wave 8192 point fft plot supply current vs sampling frequency offset error vs temperature full-scale error vs temperature supply current vs temperature sleep current vs temperature analog input leakage current vs temperature t a = 25c, av dd = dv dd = 5v, f smpl = 14ksps, unless otherwise noted. differential nonlinearity vs output code output code 0 inl (lsb) 0 0.25 0.50 4096 2309 g01 C0.25 C0.50 C1.00 1024 2048 3072 C0.75 1.00 0.75 output code 0 dnl (lsb) 0 0.25 0.50 4096 2309 g02 C0.25 C0.50 C1.00 1024 2048 3072 C0.75 1.00 0.75 frequency (khz) 0 C140 magnitude (db) C120 C100 C80 0 C40 1 3 47 2309 g03 C20 C60 2 5 6 snr = 73.4db sinad = 73.3db thd = C88db sampling frequency (ksps) 0.1 0 supply current (ma) 1.5 2.0 2.5 1 10 100 3209 g04 1.0 0.5 temperature (c) ?50 offset error (lsb) 1.5 25 2309 g05 0 ?1.0 ?25 0 50 ?0.5 ?2.0 2.0 1.0 0.5 ?0.5 75 100 125 unipolar bipolar temperature (c) C50 C25 C6 full-scale error (lsb) C2 4 0 50 75 2309 g06 C4 2 0 25 100 125 unipolar bipolar temperature (c) C50 1.0 supply current (ma) 1.2 1.6 1.8 2.0 3.0 2.4 0 50 75 2309 g07 1.4 2.6 2.8 2.2 C25 25 100 125 temperature (c) C50 0 leakage current (na) 100 300 400 500 1000 700 0 50 75 2309 g09 200 800 900 600 C25 25 100 125 ch (on) ch (off) temperature (c) C50 C25 0 sleep current (a) 4 10 0 50 75 2309 g08 2 8 6 25 100 125
LTC2309 7 2309f pin functions ch3-ch7 (pins 1-5): channel 3 to channel 7 analog inputs. ch3-ch7 can be con? gured as single-ended or differential input channels. see the analog input multiplexer section. com (pin 6): common input. this is the reference point for all single-ended inputs. it must be free of noise and should be connected to ground for unipolar conversions and midway between gnd and refcomp for bipolar conversions. v ref (pin 7): 2.5v reference output. bypass to gnd with a minimum 2.2f tantalum capacitor or low esr ceramic capacitor. the internal reference may be over- driven by an external 2.5v reference at this pin. refcomp (pin 8): reference buffer output. bypass to gnd with a 10f tantalum and 0.1f ceramic capaci- tor in parallel. nominal output voltage is 4.096v. the internal reference buffer driving this pin is disabled by grounding v ref , allowing refcomp to be overdriven by an external source. gnd (pins 9-11, pins 18-20): ground. all gnd pins must be connected to a solid ground plane. av dd (pins 12, 13): 5v analog supply. the range of av dd is 4.75v to 5.25v. bypass av dd to gnd with a 0.1f ceramic and a 10f tantalum capacitor in parallel. ad0 (pin 14): chip address control pin. this pin is con? gured as a three-state (low, high, floating) address control bit for the device i 2 c address. see table 2 for address selection. ad1 (pin 15): chip address control pin. this pin is con? gured as a three-state (low, high, floating) address control bit for the device i 2 c address. see table 2 for address selection. scl (pin 16): serial clock pin of the i 2 c interface. the LTC2309 can only act as a slave and the scl pin only accepts an external serial clock. data is shifted into the sda pin on the rising edges of the scl clock and output through the sda pin on the falling edges of the scl clock. sda (pin 17): bidirectional serial data line of the i 2 c interface. in transmitter mode (read), the conversion result is output at the sda pin, while in receiver mode (write), the d in word is input at the sda pin to con- ? gure the adc. the pin is high impedance during the data input mode and is an open-drain output (requires an appropriate pull-up device to v cc ) during the data output mode. dv dd (pin 21): 5v digital supply. the range of dv dd is 4.75v to 5.25v. bypass dv dd to gnd with a 0.1f ceramic and a 10f tantalum capacitor in parallel. ch0-ch2 (pins 22-24): channel 0 to channel 2 analog inputs. ch0-ch2 can be con? gured as single-ended or differential input channels. see the analog input multiplexer section. gnd (pin 25): exposed pad ground. must be soldered directly to ground plane.
LTC2309 8 2309f functional block diagram ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 com 2308 bd i 2 c port analog input mux refcomp internal 2.5v ref av dd dv dd gnd 12-bit sar adc LTC2309 8k gain = 1.6384x + C v ref sda scl ad1 ad0 timing diagram de? nition of timing for fast/standard mode devices on the i 2 c bus sda scl ssrps t hd(sda) s = start, sr = repeated start, p = stop t hd(dat) t su(sta) t su(sto) t su(dat) t low t hd(sda) t sp t buf t r t f t r t f t high 2309 td
LTC2309 9 2309f applications information overview the LTC2309 is a low noise, 8-channel, 12-bit succes- sive approximation register (sar) a/d converter with an i 2 c compatible serial interface. the LTC2309 includes a precision internal reference and a con? gurable 8-chan- nel analog input multiplexer (mux). the adc may be con? gured to accept single-ended or differential signals and can operate in either unipolar or bipolar mode. a sleep mode option is also provided to further reduce power during inactive periods. the LTC2309 communicates through a 2-wire i 2 c compatible serial interface. conversions are initiated by signaling a stop condition after the part has been successfully addressed for a read/write operation. the device will not acknowledge (nak) an external request until the conversion is ? nished. after a conversion is ? nished, the device is ready to accept a read/write request. once the LTC2309 is addressed for a read operation, the device begins outputting the conversion result under the control of the serial clock (scl). there is no latency in the conversion result. there are 12 bits of output data followed by 4 trailing zeros. data is updated on the falling edges of scl, allowing the user to reliably latch data on the rising edge of scl. a write operation may follow the read operation by using a repeat start or a stop condition may be given to start a new conversion. by selecting a write operation, the adc can be programmed with a 6-bit d in word. the d in word con? gures the mux and programs various modes of operation of the adc. during a conversion, the internal 12-bit capacitive charge redistribution dac output is sequenced through a successive approximation algorithm by the sar start- ing from the most signi? cant bit (msb) to the least signi? cant bit (lsb). the sampled input is successively compared with binary weighted charges supplied by the capacitive dac using a differential comparator. at the end of a conversion, the dac output balances the analog input. the sar contents (a 12-bit data word) that represent the sampled analog input are loaded into 12 output latches that allow the data to be shifted out via the i 2 c interface. programming the LTC2309 the various modes of operation of the LTC2309 are programmed by a 6-bit d in word. the sdi input data bits are loaded on the rising edge of scl during a write operation, with the s/d bit loaded on the ? rst rising edge and the slp bit on the sixth rising edge (see figure 8b in the i 2 c interface section). the input data word is de? ned as follows: s/d o/s s1 s0 uni slp s/d = single-ended/ differential bit o/s = odd/ sign bit s1 = channel select bit 1 s0 = channel select bit 0 uni = unipolar/ bipolar bit slp = sleep mode bit analog input multiplexer the analog input mux is programmed by the s/d, o/s, s1 and s0 bits of the d in word. table 1 lists the mux con? gurations for all combinations of the con- ? guration bits. figure 1a shows several possible mux con? gurations and figure 1b shows how the mux can be recon? gured from one conversion to the next. driving the analog inputs the analog inputs of the LTC2309 are easy to drive. each of the analog inputs can be used as a single-ended input relative to the com pin (ch0-com, ch1-com, etc.) or in differential input pairs (ch0 and ch1, ch2 and ch3, ch4 and ch5, ch6 and ch7). figure 2 shows how to drive com for single-ended inputs in unipolar and bipolar modes. regardless of the mux con? gura- tion, the + and C inputs are sampled at the same instant. any unwanted signal that is common to both inputs will be reduced by the common mode rejection of the sample-and-hold circuit. the inputs draw only one small current spike while charging the sample-and- hold capacitors during the acquire mode. in conversion
LTC2309 10 2309f applications information ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 com ( C ) 8 single-ended + + + + + + + 4 differential + ( C ) + + ( C ) + ( C ) + ( C ) C ( + ) C ( + ) C ( + ) C ( + ) com ( C ) combinations of differential and single-ended + + + + + + C C { { { { { { 2309 f01a ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 table 1. channel con? guration s/d o/s s1 s0 0 1 2 3 4 5 6 7 com 0000 +C 0001 +C 0010 +C 0011 +C 0100 C+ 0101 C+ 0110 C+ 0111 C+ 1000 +C 1001 +C 1010 +C 1011 +C 1100 +C 1101 +C 1110 +C 1111 +C com (unused) com ( C ) 1st conversion 2nd conversion + C + C + C + + { { { { ch2 ch3 ch4 ch5 ch2 ch3 ch4 ch5 2328 f01b com com refcomp/2 unipolar mode bipolar mode 2328 f02 + C figure 1a. example of mux con? gurations figure 1b. changing the mux assignments on the fly figure 2. driving com in unipolar and bipolar modes mode, the analog inputs draw only a small leakage cur- rent. if the source impedance of the driving circuit is low, the adc inputs can be driven directly. otherwise, more acquisition time should be allowed for a source with higher impedance. input filtering the noise and distortion of the input ampli? er and other circuitry must be considered since they will add to the adc noise and distortion. therefore, noisy input circuitry should be ? ltered prior to the analog inputs to minimize noise. a simple 1-pole rc ? lter is suf? cient for many applications. the analog inputs of the LTC2309 can be modeled as a 55pf capacitor (c in ) in series with a 100 resistor (r on ) as shown in figure 3a. c in gets switched to the selected input once during each conversion. large ? lter rc time constants will slow the settling of the inputs. it is important that the overall rc time constants be short enough to allow the analog inputs to completely settle to 12-bit resolution within the acquisition time (t acq ) if dc accuracy is important.
LTC2309 11 2309f applications information when using a ? lter with a large c filter value (e.g. 1f), the inputs do not completely settle and the capacitive input switching currents are averaged into a net dc current (i dc ). in this case, the analog input can be mod- eled by an equivalent resistance (r eq = 1/(f smpl ? c in )) in series with an ideal voltage source (v refcomp /2) as shown in figure 3b. the magnitude of the dc current is then approximately i dc = (v in C v refcomp /2)/r eq , which is roughly proportional to v in . to prevent large dc drops across the resistor r filter , a ? lter with a small resistor and large capacitor should be chosen. when running at the maximum throughput rate of 14ksps, the input current equals 1.5a at v in = 4.096v, which amounts to a full-scale error of 0.5lsb when using a ? lter resistor (r filter ) of 333. applications requiring lower sample rates can tolerate a larger ? lter resistor for the same amount of full-scale error. self heating and from damage that may occur during soldering. metal ? lm surface mount resistors are much less susceptible to both problems. dynamic performance fast fourier transform (fft) test techniques are used to test the adcs frequency response, distortion and noise at the rated throughput. by applying a low distortion sine wave and analyzing the digital output using an fft algorithm, the adcs spectral content can be examined for frequencies outside the fundamental. signal-to-noise and distortion ratio (sinad) the signal-to-noise and distortion ratio (sinad) is the ratio between the rms amplitude of the fundamental input frequency to the rms amplitude of all other fre- quency components at the a/d output. the output is band-limited to frequencies from above dc and below half the sampling frequency. figure 5 shows a typical sinad of 73.3db with a 14khz sampling rate and a 1khz input. an snr of 73.4db can be achieved with the LTC2309. v in input ch0-ch7 r on 100 c in 55pf c filter r source 2309 f03a LTC2309 figure 3a. analog input equivalent circuit v in input ch0-ch7 r eq 1/(f smpl ? c in ) v refcomp /2 c filter r filter i dc 2309 f03b LTC2309 + C figure 3b. analog input equivalent circuit for large filter capacitances figures 4a and 4b show examples of input ? ltering for single-ended and differential inputs. for the single- ended case in figure 4a, a 50 source resistor and a 2000pf capacitor to ground on the input will limit the input bandwidth to 1.6mhz. high quality capacitors and resistors should be used in the rc ? lter since these components can add distortion. npo and silver mica type dielectric capacitors have excellent linearity. carbon surface mount resistors can generate distortion from 2309 f04a ch0 com LTC2309 refcomp 2000pf 0.1f 10f 50 analog input figure 4a. optional rc input filtering for single-ended input 1000pf 2309 f04b ch0 ch1 LTC2309 refcomp 1000pf 1000pf 0.1f 10f 50 50 differential analog inputs figure 4b. optional rc input filtering for differential inputs
LTC2309 12 2309f total harmonic distortion (thd) total harmonic distortion (thd) is the ratio of the rms sum of all harmonics of the input signal to the fundamental itself. the out-of-band harmonics alias into the frequency band between dc and half the sampling frequency(f smpl /2). thd is expressed as: thd vvv v v n = ++ + 20 2 2 3 2 4 22 1 log ... where v 1 is the rms amplitude of the fundamental frequency and v 2 through v n are the amplitudes of the second through nth harmonics. internal reference the LTC2309 has an on-chip, temperature compen- sated bandgap reference that is factory trimmed to 2.5v (refer to figure 6a). it is internally connected to a reference ampli? er and is available at v ref . v ref should be bypassed to gnd with a 2.2f tantalum capacitor to minimize noise. an 8k resistor is in series with the output so that it can be easily overdriven by an external reference if more accuracy and/or lower drift are required as shown in figure 6b. the reference ampli? er gains the v ref voltage by 1.638 to 4.096v at refcomp. to compensate the reference ampli? er, bypass refcomp with a 10f ceramic or tantalum capacitor in parallel with a 0.1f ceramic capacitor for best noise performance. internal conversion clock the internal conversion clock is factory trimmed to achieve a typical conversion time (t conv ) of 1.3s and a maximum conversion time of 1.8s over the full operating temperature range. i 2 c interface the LTC2309 communicates through an i 2 c interface. the i 2 c interface is a 2-wire open-drain interface sup- porting multiple devices and multiple masters on a single bus. the connected devices can only pull the serial data line (sda) low and can never drive it high. sda is required to be externally connected to the sup- ply through a pull-up resistor. when the data line is not being driven low, it is high. data on the i 2 c bus can be transferred at rates up to 100kbits/s in the standard mode and up to 400kbits/s in the fast mode. applications information figure 5. 1khz sine wave 8192 point fft plot r2 r3 reference amp 0.1f 10f 2.2f refcomp gnd v ref r1 8k 2.5v 4.096v LTC2309 2309 f06a bandgap reference figure 6a. LTC2309 reference circuit 0.1f 10f 2309 f06b lt1790a-2.5 v out v in 5v v ref LTC2309 gnd refcomp + 2.2f 0.1f figure 6b. using the lt ? 1790a-2.5 as an external reference frequency (khz) 0 C140 magnitude (db) C120 C100 C80 0 C40 1 3 47 2309 g03 C20 C60 2 5 6 snr = 73.4db sinad = 73.3db thd = C88db
LTC2309 13 2309f each device on the i 2 c bus is recognized by a unique address stored in the device and can only operate either as a transmitter or receiver, depending on the function of the device. a device can also be considered as a master or a slave when performing data transfers. a master is the device which initiates a data transfer on the bus and generates the clock signals to permit the transfer. devices addressed by the master are consid- ered slaves. the LTC2309 can only be addressed as a slave (see table 2). once addressed, it can receive con? guration bits (d in word) or transmit the last conversion result. the serial clock line (scl) is always an input to the LTC2309 and the serial data line (sda) is bidirectional. the device supports the standard mode and the fast mode for data transfer speeds up to 400kbits/s (see timing diagram section for de? nition of the i 2 c timing). the start and stop conditions referring to figure 7, a start (s) condition is generated by transitioning sda from high to low while scl is high. the bus is considered to be busy after the start condition. when the data transfer is ? nished, a stop (p) condition is generated by transitioning sda from low to high while scl is high. the bus is free after a stop condition is generated. start and stop conditions are always generated by the master. when the bus is in use, it stays busy if a repeated start (sr) is generated instead of a stop condition. the repeated start timing is functionally identical to the start and is used for writing and reading from the device before the initiation of a new conversion. data transferring after the start condition, the i 2 c bus is busy and data transfer can begin between the master and the addressed slave. data is transferred over the bus in groups of nine bits, one byte followed by one acknowledge (ack) bit. the master releases the sda line during the ninth scl clock cycle. the slave device can issue an ack by pulling sda low or issue a not acknowledge (nak) by leaving the sda line high impedance (the external pull-up resistor will hold the line high). change of data only occurs while the scl line is low. data format after a start condition, the master sends a 7-bit ad- dress followed by a read/write (r/w) bit. the r/w bit is 1 for a read request and 0 for a write request. if the 7-bit address matches one of the LTC2309s 9 pin-selectable addresses, the adc is selected. when the adc is addressed during a conversion, it will not acknowledge r/w requests and will issue a nak by leaving the sda line high. if the conversion is complete, the LTC2309 issues an ack by pulling the sda line low. the LTC2309 has two registers. the 12-bit wide output register contains the last conversion result. the 6-bit wide input register con? gures the input mux and the operating mode of the adc. output data format the output register contains the last conversion result. after each conversion is completed, the device automati- cally enters either nap or sleep mode depending on the setting of the slp bit (see nap mode and sleep mode sections). when the LTC2309 is addressed for a read operation, it acknowledges by pulling sda low and acts as a transmitter. the master/receiver can read up to two bytes from the LTC2309. after a complete read opera- tion of 2 bytes, a stop condition is needed to initiate a new conversion. the device will nak subsequent read operations while a conversion is being performed. applications information s start condition stop condition p 2309 f07 sda scl sda scl figure 7. timing diagrams of start and stop conditions
LTC2309 14 2309f applications information the data output stream is 16 bits long and is shifted out on the falling edges of scl (see figure 8a). the ? rst bit is the msb and the 12th bit is the lsb of the conversion result. the remaining four bits are zero. figures 14 and 15 are the transfer characteristics for the bipolar and unipolar modes. data is output on the sda line in 2s complement format for bipolar readings or in straight binary for unipolar readings. input data format when the LTC2309 is addressed for a write operation, it acknowledges by pulling sda low during the low period before the 9th cycle and acts as a receiver. the master/transmitter can then send 1 byte to program the device. the input byte consists of the 6-bit d in word followed by two bits that are ignored by the adc and are considered dont cares (x) (see figure 8b). the input bits are latched on the rising edge of scl during the write operation. 12 a6 sda start by master ack by adc ack by master nak by master stop by master conversion initiated scl scl (continued) a5 a4 a3 a2 a1 a0 r/ w 3456789 123456789 123456789 2309 f08a b11 b10 read 1 byte b9 b8 b7 most significant data byte b6 b5 b4 ? ? ? ? ? ? sda (continued) ? ? ? ? ? ? b3 b2 b1 b0 least significant data byte read 1 byte address frame 12 a6 sda start by master ack by adc ack by adc conversion initiated stop by master scl a5 a4 a3 a2 a1 a0 r/ w 3456789 123456789 2309 f08b s/d o/s write 1 byte s1 s0 uni d in word slp x x address frame figure 8a. timing diagram for reading from the LTC2309 figure 8b. timing diagram for writing to the LTC2309
LTC2309 15 2309f applications information after power-up, the adc initiates an internal reset cycle which sets the d in word to all 0s (s/d = o/s = s0 = s1 = uni = slp = 0). a write operation may be performed if the default state of the adcs con? guration is not desired. otherwise, the adc must be properly addressed and followed by a stop condition to initiate a conversion. initiating a new conversion the LTC2309 awakens from either nap or sleep when properly addressed for a read/write operation. a stop command may then be issued after performing the read/write operation to trigger a new conversion. issuing a stop command after the 8th scl clock pulse of the address frame and before the completion of a read/write operation will also initiate new conversion, but the output result may not be valid due to lack of adequate acquisition time (see acquisition section). LTC2309 address the LTC2309 has two address pins (ad0 and ad1) that may be tied high, low, or left ? oating to enable one of 9 possible addresses (see table 2). in addition to the con? gurable addresses listed in table 2, the LTC2309 also contains a global address (1110111) which may be used for synchronizing mul- tiple LTC2309s or other i 2 c ltc230x sar adcs (see synchronizing multiple LTC2309s with global address call section). continuous read in applications where the same input channel is sampled each cycle, conversions can be continuously performed and read without a write cycle (see figure 9). the d in word remains unchanged from the last value written into the device. if the device has not been written to since power-up, the d in word defaults to all 0s (s/d = o/s = s0 = s1 = uni = slp = 0). at the end of a read operation, a stop condition may be given to start a new conversion. at the conclusion of the conversion cycle, the next result may be read using the method described above. if the conversion cycle is not concluded and a valid address selects the device, the LTC2309 gener- ates a nak signal indicating the conversion cycle is in progress. table 2. address assignment ad1 ad0 address low low 0001000 low float 0001001 low high 0001010 float high 0001011 float float 0011000 float low 0011001 high low 0011010 high float 0011011 high high 0101000 s conversion nap data output conversion conversion nap data output r ack read 7-bit address p s r ack 2309 f09 read 7-bit address p figure 9. consecutive reading with the same con? guration
LTC2309 16 2309f applications information continuous read/write once the conversion cycle is complete, the LTC2309 can be written to and then read from using the repeated start (sr) command. figure 10 shows a cycle which begins with a data write, a repeated start, followed by a read and concluded with a stop command. the following conversion begins after all 16 bits are read out of the device or after a stop command. the fol- lowing conversion will be performed using the newly programmed data. synchronizing multiple LTC2309s with a global address call in applications where several LTC2309s or other i 2 c sar adcs from linear technology corporation are used on the same i 2 c bus, all converters can be synchronized through the use of a global address call. prior to issu- ing the global address call, all converters must have completed a conversion cycle. the master then issues a start, followed by the global address 1110111, and a write request. all converters will be selected and ac- knowledge the request. the master then sends a write byte (optional) followed by the stop command. this will update the channel selection (optional) and simultane- ously initiate a conversion for all adcs on the bus (see figure 11). in order to synchronize multiple converters without changing the channel, a stop command may be issued after acknowledgement of the global write command. global read commands are not allowed and the converters will nak a global read request. s conversion nap data output conversion conversion data output w ack write 7-bit address sr r ack 2309 f10 read 7-bit address p s sda scl conversion nap LTC2309 data output conversion of all LTC2309s w ack write (optional) global address p LTC2309 LTC2309 2309 f11 figure 10. write, read, start conversion figure 11. syncrhonous multiple LTC2309s with a global address call
LTC2309 17 2309f applications information nap mode the adc enters nap mode after a conversion is com- plete (t conv ) if the slp bit is set to a logic 0. the sup- ply current decreases to 210a in nap mode between conversions, thereby reducing the average power dissipation as the sample rate decreases. for example, the LTC2309 draws an average of 300a at a 1ksps sampling rate. the LTC2309 keeps only the reference (v ref ) and reference buffer (refcomp) circuitry active when in nap mode. sleep mode the adc enters sleep mode after a conversion is com- plete (t conv ) if the slp bit is set to a logic 1. the adc draws only 7a in sleep mode, provided that none of the digital inputs are switching. when the LTC2309 is properly addressed, the adc is released from sleep mode and requires 200ms (t refwake ) to wake up and charge the respective 2.2f and 10f bypass capacitors on the v ref and refcomp pins. a new conversion should not be initiated before this time as shown in figure 12. acquisition the LTC2309 begins acquiring the input signal at dif- ferent instances depending on whether a read or write operation is being performed. if a read operation is being performed, acquisition of the input signal begins on the rising edge of the 9th clock pulse following the address frame as shown in figure 13a. if a write operation is being performed, acquisition of the input signal begins on the falling edge of the sixth clock cycle after the d in word has been shifted in as shown in figure 13b. the LTC2309 will acquire the signal from the input channel that was most recently programmed by the d in word. a minimum of 240ns is required to acquire the input signal before initiating a new conversion. s conversion sleep t refwake conversion r/w ack 7-bit address p 2309 f12 12 a6 sda scl a5 a4 a3 a2 a1 a0 r/ w 3456789 12 b11 acquisition begins t acq 2309 f13a b10 12 a2 a1 a0 r/ w sda scl s/d o/s s1 s0 uni x x 345 56789 6789 acquisition begins t acq 2309 f13b slp figure 12. exiting sleep mode and starting a new conversion figure 13a. timing diagram showing acquisition during a read operation figure 13b. timing diagram showing acquisition during a write operation
LTC2309 18 2309f applications information input voltage (v) 0v output code (two?s complement) ?1 lsb 2309 f14 011...111 011...110 000...001 000...000 100...000 100...001 111...110 1 lsb bipolar zero 111...111 fs/2 ? 1lsb ?fs/2 fs = 4.096v 1lsb = fs/2 12 1lsb = 1mv input voltage (v) output code 2309 f15 111...111 111...110 100...001 100...000 000...000 000...001 011...110 011...111 fs ? 1lsb 0v unipolar zero fs = 4.096v 1lsb = fs/2 12 1lsb = 1mv figure 14. bipolar transfer characteristics (2s complement) figure 15. unipolar transfer characteristics (straight binary) board layout and bypassing to obtain the best performance, a printed circuit board with a solid ground plane is required. layout for the printed board should ensure digital and analog signal lines are separated as much as possible. care should be taken not to run any digital signals alongside an analog signal. all analog inputs should be shielded by gnd. v ref , refcomp and av dd should be bypassed to the ground plane as close to the pin as possible. maintaining a low impedance path for the common return of these bypass capacitors is essential to the low noise operation of the adc. these traces should be as wide as possible. see figure 16 for a suggested layout. figure 16. suggested layout
LTC2309 19 2309f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description uf package 24-lead plastic qfn (4mm 4mm) (reference ltc dwg # 05-08-1697) 4.00 0.10 (4 sides) note: 1. drawing proposed to be made a jedec package outline mo-220 variation (wggd-x)to be approved 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side, if present 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 2423 1 2 bottom viewexposed pad 2.45 0.10 (4-sides) 0.75 0.05 r = 0.115 typ 0.25 0.05 0.50 bsc 0.200 ref 0.00 C 0.05 (uf24) qfn 0105 recommended solder pad pitch and dimensions 0.70 0.05 0.25 0.05 0.50 bsc 2.45 0.05 (4 sides) 3.10 0.05 4.50 0.05 package outline pin 1 notch r = 0.20 typ or 0.35 s 45 chamfer
LTC2309 20 2309f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2008 lt 0208 ? printed in usa related parts typical application part number description comments ltc1417 14-bit, 400ksps serial adc 20mw, unipolar or bipolar, internal reference, ssop-16 package ltc1468/ltc1469 single/dual 90mhz, 22v/s, 16-bit accurate op amps low input offset: 75v/125v ltc1609 16-bit, 200ksps serial adc 65mw, con? gurable bipolar and unipolar input ranges, 5v supply ltc1790 micropower low dropout reference 60a supply current, 10ppm/c, sot-23 package ltc1850/ltc1851 10-bit/12-bit, 8-channel, 1.25msps adcs parallel output, programmable mux and sequencer, 5v supply ltc1852/ltc1853 10-bit/12-bit, 8-channel, 400ksps adcs parallel output, programmable mux and sequencer, 3v or 5v supply ltc1860/ltc1861 12-bit, 1-/2-channel 250ksps adcs in msop 850a at 250ksps, 2a at 1ksps, so-8 and msop packages ltc1860l/ltc1861l 3v, 12-bit, 1-/2-channel 150ksps adcs 450a at 150ksps, 10a at 1ksps, so-8 and msop packages ltc1863/ltc1867 12-/16-bit, 8-channel 200ksps adcs 6.5mw, unipolar or bipolar, internal reference, ssop-16 package ltc1863l/ltc1867l 3v, 12-/16-bit, 8-channel 175ksps adcs 2mw, unipolar or bipolar, internal reference, ssop-16 package ltc1864/ltc1865 16-bit, 1-/2-channel 250ksps adcs in msop 850a at 250ksps, 2a at 1ksps, so-8 and msop packages ltc1864l/ltc1865l 3v, 16-bit, 1-/2-channel 150ksps adcs in msop 450a at 150ksps, 10a at 1ksps, so-8 and msop packages ltc2302/ltc2306 12-bit, 1-/2-channel 500ksps spi adcs in 3mm 3mm dfn 14mw at 500ksps, single 5v supply, software compatible with ltc2308 ltc2308 12-bit, 8-channel 500ksps spi adc 5v, internal reference, 4mm 4mm qfn package, software compatible with ltc2302/ltc2306 ltc2453 easy-to-use, ultra-tiny 16-bit i 2 c delta sigma adc 2lsb inl, 50na sleep current, 60hz output rate, 3mm 2mm dfn package ltc2487/ltc2489/ ltc2493 2-/4-channel easy drive i 2 c delta sigma adcs 16-/24-bits, pga and temperature sensor, 15hz output rate, 4mm 3mm dfn packages ltc2495/ltc2497/ ltc2499 8-/16-channel easy drive i 2 c delta sigma adcs 16-/24-bits, pga and temperature sensor, 15hz output rate, 5mm 7mm qfn packages ch1 ch2 ch3 ch4 ch5 ch6 ch7 com 2309 ta02 i 2 c port analog input mux refcomp control logic (fpga, cpld, dsp , etc) internal 2.5v ref av dd dv dd 5v 10v C10v 10v input signal gnd LTC2309 0.1 f 12-bit sar adc + C 2.2f 10f 0.1 f 10f 10f 0.1 f 1 f 0.1 f 47pf 7 45 6 8 1 9 10 100 450k lt1790-2.5 lt1991 5v in out gnd 50k 150k 450k 150k 450k 4pf v ref sda scl 1.7k 1.7k ad1 ad0 ch0 450k 4pf 3 2 50k C + lt1991 driving the LTC2309 with 10v input signals using a precision attenuator

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